NXP Semiconductors
Noida, Uttar Pradesh, India Posted 4d ago
Manage and lead Process Design Kit Physical Verification team at NXP Semiconductors. The candidate will drive PDK PV testing, customer support, and tool evaluations.
Key Responsibilities
Development of Calibre physical verification decks for cmos, FinFET, bulk, SOI, RF, bicmos and powermos technologies including DRC, LVS, PERC, Fill LPE, and shape generation decks and scripts.
Development and validation of PV tools and flows using LLM based AI tools, recent EDA AI tools like Calibre AI, Virtuoso AI.
Development of the Process Design Kit infrastructure for PV tools, flows and utilities.
Testing, validation, customer support and new tool/methods evaluations.
Automation of deck and techFiles generation and validation.
Requirements
15+ years of experience with PDK Physical Verification rule deck development and/or support.
In depth knowledge of foundry based and EDA tools based process variation formats e.g. ICT, IRCX.
Experience with Calibre SVRF/TVF rule deck coding or Cadence PVS/Assura rule deck coding.
Experience with tools like Calibre, CalibreXRC, Assura, Cadence PVS, Synopsys ICV, Virtuoso.
BE/B.Tech/ME/M.Tech in Electrical or Electronics Engineering.
