Senior ASIC Design Engineer - GPU Core Pipeline IP

NVIDIA is seeking a Design Engineer to design and implement the next generation of control subsystems for industry-leading GPUs.

Key Responsibilities

• Contribute to the design and implementation of graphics and compute features within an IP.

• Responsible for micro-architecture and RTL design of GPU ASICs.

• Develop RTL using Verilog and SystemVerilog while collaborating on design specifications.

• Ensure designs meet performance, power, area, and timing goals.

• Participate in silicon bring-up, post-silicon debug, and performance analysis.

Requirements

• B.Tech or M.Tech with 5+ years of relevant experience.

• Familiarity with Verilog, C++, and OOPs concepts.

• Experience in RTL design and micro-architecture development.

• Good understanding of digital design fundamentals and computer architecture.