Micron
Hyderabad, Telangana, India Posted 2d ago
Micron Technology is hiring a Senior Engineer for CAD Physical Verification to evaluate, improve EDA, and debug both in-house and commercial Electronic Design Automation tools and flows for CMOS integrated circuits. You will work closely with memory layout teams to increase productivity and efficiency.
Key Responsibilities
Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future.
Proactively identify problem areas for improvement, propose, and develop innovative solutions.
Develop methodologies for highly reliable layout with faster Time to Market approach.
Lead layout flows implementation using AI-assisted and automated workflows, applying copilot-based assistants, agentic AI flows, and rule-aware automation.
Continuously evaluate and implement new tools and technologies to improve the current layout development flows.
Provide guidance and mentorship to junior members of the team.
Requirements
A bachelor’s or a master’s degree in Electronics, Electrical or Computer Engineering.
5+ years of experience in Layout automation, Physical Verification, or related domains.
Experience in customizing a design environment, automation methodologies and utilities to increase memory layout productivity.
Working experience in Place and Router flows for custom memory layouts with industry standard tools like Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools etc.
Working of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna Calibre/ICV rule deck issues.
Good understanding of advanced CMOS process manufacturing and layout design rules, EMIR, RC-Extraction, ESD, and Latch-up.
Proficiency in programming languages including Skill (Cadence), Perl, Python, Tcl.
Working knowledge of Linux is a must.
Preferred Qualifications
Working experience in PDN analysis tools like Totem/VoltusXFA/XA
Proven expertise in defining, developing, and scaling AI-driven automation
