Firmware Engineer - High Speed SERDES PHY

Cadence Design Systems is seeking a Firmware Engineer II to join a dynamic and growing team of experienced engineers developing physical IP for industry-standard high-speed serial-link protocols. You will contribute during all phases of firmware development for high speed SERDES from architecture development to implementation, verification, testing and customer deployment.

Key Responsibilities

• Contribution during firmware architecture development and implementation of the defined firmware features.

• Working closely with verification team to debug and fix the FW issues found with verification simulations.

• Involvement during post-silicon testing and validation to identify any FW and HW related functionality and performance issues and implement any necessary FW improvements to address these issues.

• Interaction with Product Engineering, System Validation and Design team to debug IP issues in the field and provide hot fixes.

• Help to build system level prototype control software to develop/validate adaptation, equalization, and control algorithms for high speed SERDES.

• Implement assigned FW features and work closely with verification and validation team to ensure the functionality and robustness of the implemented features.

• Support of Validation team during electrical and system characterization.

• Support of Product Engineering team during customer deployment of the IP.

Requirements

• Solid programming knowledge in C/C++ and Python

• Understanding of wireline communication principles

• Knowledge in mixed signal circuit design and digital signal processing techniques

• Strong problem solving and communication skills

• B.Tech or M.Tech in Electrical or Computer Engineering with 2-4 years of experience